Many of today's high performance data processing systems suffer from the problem of inefficient usage of cache memory capacity. The inefficiency is largely attributable to the fact that generally different applications achieve desired hit rates when different cache organizations are employed. For some applications, a two-way or direct-mapped cache may be sufficient,therefore, extra cache sets provide only a small increase in the hit rates. For example, if an x-way cache provides a sufficient hit rate, where x=1, then (n-x) cache sets are underutilized (where n is an integer greater than or equal to 2). Accordingly, applications with different hit rate requirements can free cache sets for usage as random access memory (RAM).
Further exacerbating the problem in conventional caches, is the high-overhead associated with usage of a tag store array. Typically, the size of the tag store array required to provided the desired cache hit rate is on the order of two times the number of bytes of actual data stored in a line store array. Consequently, if only "x" sets are required to provide the desired hit rate, then 2(n-x) times the number of bytes of actual data stored in the line store array are wasted. Essentially, each underutilized cache set could potentially provide twice as many bytes of actual information storage if used as a RAM bank. Known data processors provide a mechanism, (i.e. a bit to disable cache filling) which allows the system software to load the cache memory and use the cache memory as a static RAM. This "freeze" bit may allow the processor to disable one cache set at a time. Thus, it is desirable to provide a cache memory which overcomes the foregoing problems.